Application framework for selection and method discussions; not a customer test report.
Purpose
Cross-sections of PCBs, solder joints, packages and interfaces.
Preparation route
Locate the target layer or connection before sectioning and progressive removal. Evaluate cold mounting and thermal sensitivity, and control relief between materials.
Checkpoints
Avoid overshooting the target. Distinguish smearing and preparation damage from original defects. Etching is not automatically required.
Equipment stages
Cutting → Mounting → Grinding and polishing → appropriate microscopy and testing.
Record sampling position, consumables, actual settings and images. Evaluate using the agreed method.
Typical inspection scenarios
Cross-section of BGA solder joints and multilayer PCB vias
- Challenge
- A PCB is a mixed multilayer system of soft copper, brittle resin and glass fiber: copper smears easily while resin chips at the edges; heat and stress from sectioning can crack solder joints and cause delamination, destroying the true appearance of the IMC layer and voids.
- Preparation & method
- Section perpendicular to the target joint with a low-speed precision saw using a diamond blade at low feed with ample coolant. Cold mount with low-viscosity epoxy under vacuum impregnation to avoid thermal damage from hot mounting and to infiltrate micropores for reinforcement. Start fine grinding at P800 to prevent edge chipping and proceed to P2000; polish with 1 μm diamond followed by 0.05 μm colloidal silica, then examine unetched for void fraction, IMC thickness and copper plating continuity.
- Reference standards
- IPC-A-600 Acceptability of Printed Boards; IPC-TM-650 Test Methods Manual (microsectioning); ASTM E3 Standard Guide for Preparation of Metallographic Specimens
Nano-silver sintered die-attach layer and DBC substrate solder layer of an IGBT power module
- Challenge
- The sintered silver layer contains 5%–15% process porosity; soft silver smears and pore edges round off during preparation, falsifying porosity and interface-coverage quantification; the Si die, silver layer and DBC (Al₂O₃/AlN ceramic) stack differ greatly in hardness, so sectioning easily causes die chipping and interlayer delamination.
- Preparation & method
- Section vertically through the center of the target die on a low-speed precision diamond saw at low feed with ample coolant. Vacuum-impregnate with low-viscosity epoxy cold mounting resin so it infiltrates sintering pores and interlayer gaps to consolidate the stack. Fine-grind gently from P800 to P2000 to avoid delamination; polish with 1 μm diamond and finish with 0.05 μm colloidal silica. Examine unetched under bright field for pore morphology and distribution in the silver layer and the die/silver and silver/DBC interface coverage, quantifying porosity and coverage by image analysis; measure silver and solder layer hardness by micro-Vickers (HV0.01–0.05); after die-shear testing, re-examine the shear surface metallographically to determine the failure mode (cohesive/interfacial).
- Reference standards
- IPC-TM-650 Test Methods Manual (microsectioning); GB/T 4937 Semiconductor devices — Mechanical and climatic test methods; ASTM E3 Standard Guide for Preparation of Metallographic Specimens
Scenarios are method examples, not customer test reports; confirm the process per specimen.
MICROCRE learning notes · confirm the method for the specimen.